Senior Silicon Physical Design, Layout Engineer

BLUE ORIGIN

Senior Silicon Physical Design and Layout Engineer designing advanced integrated circuits for space-based communications. Collaborating with cross-functional teams in a fast-paced environment to meet mission-critical challenges.

Posted 6/23/2026full-timeAustin • California, Texas, Washington • 🇺🇸 United StatesSenior💰 $197,529 - $276,539 per yearWebsite

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Hard Skills

ASIC designphysical designlayout techniquesfloor planningpower distributionclock tree synthesisroutingtiming closuresignal integrity analysisdesign for test (DFT)

Soft Skills

collaborationdocumentationproblem-solvinginnovation

Tools & Technologies

CadenceSynopsysMentorEDA toolsdata analytics

Industry Keywords

mixed-signal designsspace qualificationradiation tolerancereliabilitysemiconductor fabricationdesign rulespower analysisoptimization techniques

About the role

Key responsibilities & impact

Execute physical design and layout of ASICs that integrate both analog and digital processing
Implement floor planning, power distribution, clock tree synthesis, and routing for complex mixed-signal designs
Develop ASICs that meet the stringent standards of space qualification, ensuring high performance and efficiency
Perform timing closure, signal integrity analysis, and physical verification (DRC/LVS/ERC)
Implement advanced RF processing technologies that support missions with reduced size, weight, and power (SWaP)
Optimize layouts for radiation tolerance and reliability in the space environment
Collaborate with front-end designers to ensure design intent is preserved through implementation
Perform static timing analysis and address timing violations
Utilize data analytics to optimize ASIC performance and drive innovation
Work with semiconductor foundries to ensure manufacturability and yield optimization
Implement design for test (DFT) structures and methodologies
Document physical design processes, methodologies, and results
Support post-silicon validation and debug activities.

Requirements

What you’ll need

B.S. degree in Electrical Engineering, Computer Engineering, or related field
7+ years of experience in physical design and layout of ASICs
Demonstrated expertise in digital and analog layout techniques
Experience with industry-standard EDA tools for physical design (Cadence, Synopsys, or Mentor)
Knowledge of semiconductor fabrication processes and design rules
Understanding of timing closure and signal integrity challenges
Experience with power analysis and optimization techniques.

Benefits

Comp & perks

Medical, dental, vision, basic and supplemental life insurance
Paid parental leave
Short and long-term disability
401(k) with a company match of up to 5%
Education Support Program
Stock Options for all regular employees (working at least 20 hours/week)
Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.