Design Engineer – AI SoC Development

Intel Corporation

RTL Design Engineer at Intel focusing on AI SoC development and integration of advanced components. Collaborating with teams and ensuring high-quality design and validation for innovative hardware solutions.

Posted 6/29/2026full-timeFolsom • California, Oregon, Texas • 🇺🇸 United StatesMid-LevelSenior💰 $164,470 - $232,190 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in RTL design and implementation for ASIC/SoC development, with a strong focus on Verilog/System Verilog coding, timing closure methodologies, and integration of IP blocks. Proficient in applying design optimization strategies and collaborating with verification teams to ensure design integrity.

Highest-signal resume keywords

RTL Design and ImplementationVerilog/System Verilog ProficiencySynthesis Tools ExperienceStatic Timing Analysis (STA)SoC System Integration

ATS Keywords

Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills

RTL CodingLogic DesignTiming ClosurePower OptimizationClock Domain CrossingFormal VerificationHigh-Speed Design TechniquesLow-Power Design TechniquesScripting (Python, TCL)Quality Checks

Tools & Technologies

Synthesis ToolsStatic Timing Analysis ToolsFormal Verification Tools

Industry Keywords

ASIC DevelopmentSoC DesignIP IntegrationEmbedded Processor ArchitecturesStandard Bus Protocols (AXI, AHB)

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

develop logic design, register transfer level (RTL) coding, and simulation for SoC designs
integrate IP blocks and subsystems into full chip SoC or discrete component designs
participate in defining architecture and microarchitecture features
perform quality checks across various logic design aspects from RTL to timing/power convergence
apply strategies, tools, and methods to write RTL and optimize logic
ensure design integrity for physical implementation
work closely with verification teams, review verification plans and resolve failing RTL tests
follow secure development practices and collaborate with IP providers

Requirements

What you’ll need

Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science
4+ years of experience in RTL design and implementation for ASIC/SoC development
Proficiency in Verilog/System Verilog for RTL coding and design
Experience with synthesis tools and timing closure methodologies
Understanding of clock domain crossings, power optimization, and timing closure
Exposure to SoC system integration and CPU subsystem design
Familiarity with standard bus protocols (AXI, AHB, etc.) and embedded processor architectures
Knowledge of high-speed and low-power design techniques
Experience with static timing analysis (STA) tools and methodologies
Hands-on experience with formal verification tools and techniques
Basic scripting skills (Python, TCL, etc.) for automation

Benefits

Comp & perks

competitive pay
stock bonuses
health
retirement
vacation