Design Verification Architect

Intel Corporation

Design Verification Architect at Intel responsible for defining and implementing verification strategies for silicon design. Collaborating with architecture and design teams to optimize verification methodologies and processes.

Posted 7/7/2026full-timeFolsom • California • 🇺🇸 United StatesMid-LevelSenior💰 $190,610 - $269,100 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in silicon design development and validation methodologies, with a strong focus on UVM and formal verification approaches. Proficient in hardware simulation tools and programming languages such as C/C++/Python and System Verilog, while effectively collaborating with cross-functional teams to enhance design integrity and security.

Highest-signal resume keywords

Silicon Design DevelopmentUVM-Based Test BenchesC/C++/Python ProficiencyFunctional SimulationSecurity Validation Strategy

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Silicon DesignVerification MethodologiesTest Bench ArchitectureFunctional CoverageCode CoverageSimulation Environment DevelopmentFailure AnalysisCoverage AnalysisMicroarchitectural FeaturesIP Validation Tools

Soft Skills

Team CollaborationProblem-SolvingAttention to Detail

Tools & Technologies

Hardware Simulation ToolsUVMOVMFormal Verification Tools

Industry Keywords

ElectronicsComputer EngineeringGraphics ArchitectureValidation Infrastructure

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Defines, architects, and documents verification strategy and methodologies for implementing and verifying the silicon design in the most optimal manner.
Architects the testbenches and develops universal verification methodology (UVM) or formal based verification approaches.
Integrates the block testbench in chiplevel UVM environment and verifies integration.
Develops test strategy, test bench architecture, and test plans for design blocks to conform to specifications.
Enables interaction with analog and digital teams and supports postsilicon validation activities.
Collaborates with the architecture and design team to create random test generation plans, runs functional simulation to identify gaps in design specification, and conducts failure analysis, coverage analysis, and closure.
Defines and develops the security validation strategy and validation infrastructure to incorporate security tools and methods to improve security coverage.

Requirements

What you’ll need

Bachelor's degree in Electronics, Computer Engineering, or related field and at least 6+ years of experience OR a Master's degree in the mentioned fields with 4+ years of experience in silicon design development, frontend validation methodologies, simulation environment development (testbench, checker), and simulation/emulation debugging.
Proficiency in functional and code coverage closures.
Expertise in hardware simulation and validation tools, with strong technical proficiency in C/C++/Python and System Verilog.
Familiarity with IP validation tools, processes, and protocols.
Experience with OVM/UVM-based test benches and formal verification tools.
Deep knowledge of graphics architecture and designs, with an understanding of microarchitectural features.
Strong team collaboration skills, problem-solving ability, and attention to detail.
Desire to work on high-impact projects that challenge and expand your technical capabilities.

Benefits

Comp & perks

competitive pay
stock bonuses
benefit programs which include health
retirement
vacation