Physical Design Engineer

Intel Corporation

Physical Design Engineer at Intel, focusing on designing custom IP and SoC implementations. Contributing to innovative semiconductor products and optimizing critical parameters for success.

Posted 7/8/2026full-timeBeaver Brook • Arizona, Massachusetts • 🇺🇸 United StatesJunior💰 $91,150 - $149,150 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in physical design implementation for custom IP and SoC designs, utilizing industry-standard EDA tools and methodologies to optimize designs and ensure compliance with product specifications.

Highest-signal resume keywords

Physical Design ImplementationEDA Tools ProficiencyTiming ClosureRTL Design ExperienceScripting in TCL

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Physical Design ImplementationTiming AnalysisLayout VerificationClock Tree SynthesisFloor PlanningPower Integrity AnalysisLogic SynthesisStatic Timing AnalysisDesign Closure

Soft Skills

CollaborationProblem-Solving

Tools & Technologies

EDA Tools

Industry Keywords

Custom IPSoC DesignsElectrical EngineeringComputer Engineering

About the role

Key responsibilities & impact

Perform physical design implementation of custom IP and SoC designs
Conduct verification and signoff processes, including formal equivalence verification, reliability verification, and more
Analyze results and recommend fixes for violations to meet product design specifications
Optimize designs to enhance product-level parameters
Develop and improve physical design methodologies and flow automation
Collaborate with multi-disciplinary teams to address challenges in physical design

Requirements

What you’ll need

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related specialized field of study with 3+ years of hands-on experience in physical design implementation for custom IP or SoC designs OR a Master's degree with 2+ years of hands-on experience
Proficiency in industry-standard EDA tools for synthesis, place and route, timing analysis, and layout verification
Experience in physical design flows, including clock tree synthesis, floor planning, timing closure, and power integrity analysis
Physical design experience in integrated circuit design tools including logic synthesis, place and route, static timing analysis, and design closure
Design experience with RTL design
Experience with scripting in an interpreted language (TCL)

Benefits

Comp & perks

competitive pay
stock bonuses
benefit programs which include health, retirement, and vacation