Principal Engineer, AMS IP Architecture

Intel Corporation

Principal Engineer in AMS IP Architecture at Intel, defining and driving next-generation analog and mixed-signal IP architectures. Collaborating with teams and innovating for high-performance computing and ultra-low power products.

Posted 7/16/2026full-timeSanta Clara • Arizona, California, Oregon, Texas • 🇺🇸 United StatesLead💰 $220,920 - $311,890 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in Analog and Mixed-Signal IP Architecture, focusing on high-speed communications and signal processing. Proficient in developing and validating SerDes models and calibration techniques to optimize performance and power efficiency.

Highest-signal resume keywords

SerDes Modeling in MATLABHigh-Speed Analog CMOS DesignDSP Techniques for SerDes EqualizationLink Budget Analysis for NRZ/PAM4 SignalingSilicon Measurements Correlation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Signal Processing AlgorithmsCalibration TechniquesEnd-to-End PCIe Gen7/Gen8 SerDes Models128Gbps+ Link SimulationsReal-Time Calibration DSP AlgorithmsEqualization Techniques (FFE, DFE, CTLE)CDR Loop DynamicsJitter Tolerance

Soft Skills

Collaboration with Cross-Functional TeamsProblem-SolvingTechnical Issue Resolution

Tools & Technologies

MATLABSimulinkCVerilog-ASystemVerilog

Industry Keywords

Analog CircuitsHigh-Speed CommunicationsSignal ProcessingCommunications TheoryProtocol Specifications

About the role

Key responsibilities & impact

As a Principal Engineer in AMS IP Architecture, you will play a pivotal role in defining and driving next-generation analog and mixed-signal (AMS) IP architectures
Apply your expertise to develop innovative architectures, signal processing algorithms, and calibration techniques to optimize performance, power, and area across a range of applications
Collaborate with cross-functional teams to ensure Intel's AMS solutions deliver exceptional results for diverse segments
Architected end-to-end PCIe Gen7/Gen8 SerDes models (NRZ/PAM4) in MATLAB/Simulink
Executed 128Gbps+ link simulations to validate protocol specs and mitigate margin risks prior to tapeout
Designed real-time calibration and adaptation DSP algorithms balancing convergence speed, stability, and power
Validated simulation models against lab silicon measurements
Partnered with analog, digital, and hardware teams on circuit trade-offs, logic design, and lab bringup
Resolved technical field issues and performed custom link budget analyses for client channel/module configurations
Evaluated early-stage protocol updates and design specs to guarantee system-level feasibility

Requirements

What you’ll need

M.Sc. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field with focus on high-speed communications, analog circuits, or signal processing
Deep expertise in one or more of the following: SerDes modeling in MATLAB or Simulink, high-speed analog CMOS design, DSP techniques for SerDes equalization and timing recovery, or communications theory including equalization, coding, and noise filtering
Experience analyzing and closing link budgets for NRZ or PAM4 signaling at 100Gbps or higher, accounting for transmitter impairments, channel loss, reflection, crosstalk, and receiver noise
Hands-on work with SerDes transmitter and receiver architectures, equalization techniques such as FFE, DFE, and CTLE, or CDR loop dynamics and jitter tolerance
Ability to correlate models with silicon measurements, debug discrepancies systematically, and update models to reflect real-world behavior
Familiarity with C, Verilog-A, or SystemVerilog for co-simulation or algorithm prototyping is a plus

Benefits

Comp & perks

competitive pay
stock bonuses
health
retirement plans
vacation