Senior SoC Subsystem and I/O Architect

NVIDIA

Senior SoC Subsystem & I/O Architect defining high-level architecture for next-generation AI and high-performance computing products at NVIDIA. Collaborating across teams for innovative solutions in cutting-edge technology.

Posted 6/27/2026full-timeRemote • Massachusetts, Texas • 🇺🇸 United StatesSenior💰 $184,000 - $356,500 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

The ideal candidate must demonstrate expertise in SoC architecture and subsystem development, with a strong ability to collaborate across multiple teams to drive architectural decisions and validate subsystem behavior effectively.

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

SoC ArchitectureSubsystem ArchitectureIO ArchitectureInterconnect ArchitectureC++SystemCPythonMemory OrderingCoherencyError Management

Soft Skills

Strong Communication AbilitiesCollaborationHarmonization of Architecture DecisionsProblem SolvingLeadership

Tools & Technologies

PCIeCXLNVLinkUCIeAXICHINoC FabricsFirmwareValidation StrategiesVerification Plans

Certifications & Qualifications

BS in Electrical EngineeringMS in Electrical EngineeringPhD in Electrical EngineeringEquivalent Experience

Industry Keywords

High-Performance SystemsFunctional ModelsArchitectural ModelsGolden ModelsBootResetCapability DiscoveryPower Management ArchitectureRASDebug

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Define high-level SoC subsystem architecture for LPU products
Convert LPU product requirements into architectural specifications for uncore, IO, memory, firmware-facing, boot, reset, safety, fault tolerance, diagnostic, and power regulation subsystems
Collaborate intimately with IP teams to develop detailed build documents for PCIe/CXL, NVLink/NVLink-C2C, UCIe, AXI/CHI, NoC fabrics, memory controllers, coherency blocks, MMUs/IOMMUs, boot, reset, and associated SoC infrastructure
Specify subsystem behavior encompassing enumeration, capability discovery, configuration flows, sequence control of memory operations, data consistency, address mapping, interrupt handling, virtualization, error handling, and firmware/software-visible controls
Build or guide functional and architectural models from specifications, using C++, SystemC, Python, or similar languages
Use models to validate architecture intent, subsystem behavior, configuration sequences, and IP interactions before RTL or silicon is available
Drive tradeoffs across bandwidth, latency, power, area, timing, scalability, reliability, security, debuggability, and software usability
Review IP specifications, subsystem architecture documents, model behavior, verification plans, and validation strategies
Collaborate with architecture, IP, firmware, software, RTL, verification, platform, and post-silicon teams to bring architecture decisions to completion

Requirements

What you’ll need

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience
8+ years of proven experience in SoC architecture, subsystem architecture, IO architecture, interconnect architecture, GPU/CPU architecture, accelerator architecture, or high-performance systems
Strong understanding of SoC architecture and uncore subsystem development
Extensive understanding of IO and interconnect cores including PCIe, CXL, NVLink, NVLink-C2C, UCIe, AXI, CHI, or NoC fabrics
Experience working from product requirements to architecture requirements and IP/subsystem specifications
Experience crafting functional models, architectural models, golden models, or C/SystemC models from architecture specifications
Solid grasp of memory ordering, coherency, address translation, interrupts, virtualization, MMUs/IOMMUs, enumeration, configuration, and error management
Solid knowledge of boot, reset, firmware handoff, capability discovery, security, RAS, debug, and power-management architecture
Strong communication abilities and capability to harmonize architecture decisions across IP, firmware, software, verification, and product groups.

Benefits

Comp & perks

Competitve salaries
Equity
Comprehensive benefits package
Opportunities for professional growth
Flexible working arrangements