Integrated Circuit Design Verification Engineer

Snap Inc.

Integrated Circuit Design Verification Engineer working with multi-disciplinary team on AR display Integrated Circuits at Snap Inc. Developing verification testbenches and plans, collaborating with various engineering teams.

Posted 7/2/2026full-timeRemote • Washington • 🇺🇸 United StatesSeniorLead💰 $173,000 - $259,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in ASIC Design Verification with a strong focus on UVM and SystemVerilog methodologies, complemented by extensive experience in digital functional simulation and automation scripting. Proficient in utilizing Siemens Questa for verification and debugging tasks within a collaborative multi-disciplinary team environment.

Highest-signal resume keywords

ASIC Design VerificationUVMSystemVerilogSiemens QuestaScripting and Automation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

UVM-Based TestbenchesAssertion-Based TestbenchesDigital Functional SimulationVerilog RTL Coding PracticesTCLMakePerlPythonShell ScriptsLinux Environment

Tools & Technologies

Siemens Questa Tool Set

Certifications & Qualifications

BSEEMSEE

Industry Keywords

Integrated CircuitsARVerification Test PlansFunctional CoverageCode Coverage

Tech Stack

Tools & technologies

LinuxPerlPython

About the role

Key responsibilities & impact

Work as part of a multi-disciplinary team designing display Integrated Circuits for AR
Work closely with digital design, analog logic, software and verification engineers
Develop and implement UVM-based and assertion-based testbenches
Create and execute verification test plans, including functional coverage and code coverage
Utilize Siemens Questa tool set for verification and debug tasks
Specify and configure tools and create automation

Requirements

What you’ll need

BSEE or MSEE or relevant years of experience
10+ years of experience in ASIC Design Verification
Strong knowledge of UVM and SystemVerilog for advanced verification methodologies
Strong knowledge of digital functional simulation, and tools such as Siemens Questa
Strong knowledge of good Verilog RTL coding practices
Scripting and automation, such as TCL, Make, Perl, Python and Shell scripts in Linux environment

Benefits

Comp & perks

paid parental leave
comprehensive medical coverage
emotional and mental health support programs
compensation packages that let you share in Snap’s long-term success