DV DFT Engineer

Cisco

Design Verification Engineer pushing boundaries at Cisco, focusing on DFT activities and methodologies. Collaborating with cross-functional teams on advanced silicon features.

Posted 6/28/2026full-timeTel Aviv-Yafo • 🇮🇱 IsraelMid-LevelSeniorWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in DFT verification activities, including the development of verification plans, environments, and methodologies. Proficient in SystemVerilog and UVM, with a strong understanding of DFT concepts and SoC-level verification.

Highest-signal resume keywords

DFT VerificationSystemVerilogUVM-Based VerificationDFT DV MethodologiesSoC Verification

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

DFT Architecture VerificationVerification Plans DevelopmentAssertions DevelopmentCoverage ModelsDebug FlowsScan InsertionMemory BISTATPGBoundary ScanSilicon Test Flows

Soft Skills

Strong Communication SkillsCross-Functional CollaborationAttention to DetailOwnership MindsetMotivation to Learn

Certifications & Qualifications

B.Sc. in Electrical EngineeringM.Sc. in Electrical EngineeringB.Sc. in Computer EngineeringM.Sc. in Computer Engineering

Industry Keywords

DFTSoC-Level Test FeaturesNetworking SiliconHigh-Performance AI-Driven SiliconChip Architecture

About the role

Key responsibilities & impact

Establish and drive DFT verification activities within the Cisco SiliconOne DFT team.
Develop verification plans, environments, checkers, assertions, and coverage models for DFT features.
Verify DFT architecture and implementation in close collaboration with DFT, design, architecture, and verification teams.
Work on verification of scan, MBIST, IJTAG/JTAG, test access mechanisms, DFT controllers, and related SoC-level test features.
Debug complex pre-silicon issues across RTL, verification environments, and DFT logic.
Contribute to scalable methodologies, reusable verification components, and best practices for DFT DV.
Help bridge between general DV methodologies and DFT-specific design and verification needs.

Requirements

What you’ll need

B.Sc . or M.Sc . in Electrical Engineering, Computer Engineering, or a related field
5+ years of experience in design verification roles
Strong experience with SystemVerilog and UVM-based verification environments
Experience developing verification plans, coverage models, assertions, and debug flows
Strong communication skills and ability to work closely with cross-functional teams
Motivation to learn DFT concepts and become a key contributor in the DFT DV domain.
Experience with DFT DV, including verification of scan, MBIST, JTAG/IJTAG, ATPG-related logic, or test controllers.
Familiarity with DFT concepts such as scan insertion, memory BIST, ATPG, boundary scan, and silicon test flows.
Experience with complex SoC verification, networking silicon, or high-performance AI-driven silicon.
System-level understanding of large-scale chip architecture and integration.
Ability to build new methodologies and establish verification activity from the ground up.
High attention to detail, ownership mindset, and willingness to grow into new technical domains.

Benefits

Comp & perks

Flexible work arrangements
Professional development opportunities