ASIC DFT Engineer

Cisco

ASIC Engineer focusing on Design-for-Test within Silicon One development organization. Collaborate on chip architecture and work on innovative hardware platforms at Cisco.

Posted 6/30/2026full-timeSan Jose • California, Texas • 🇺🇸 United StatesMid-LevelSenior💰 $152,500 - $219,200 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in Hardware Design-for-Test (DFT) implementation, including JTAG protocols, Scan and BIST architectures, and post-silicon validation. Proficient in collaborating with multi-functional teams to develop innovative DFT IP and validate test logic throughout the design process.

Highest-signal resume keywords

Hardware Design-For-Test (DFT)JTAG ProtocolsBIST ArchitecturesATPG and EDA ToolsPost-Silicon Validation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

DFT ImplementationTest Logic IntegrationGate Level SimulationDebugging with VCSMemory BISTBoundary ScanATE PatternsP1687Innovative DFT DevelopmentSilicon Engineering

Soft Skills

CollaborationProblem-SolvingMinimal Mentorship

Tools & Technologies

TestMaxTetramaxTessent Tool SetsPrimeTime

Certifications & Qualifications

Bachelor's Degree in Electrical EngineeringMaster's Degree in Computer Engineering

Industry Keywords

Silicon Device ModelsBare DieStacked DieIn-System TestDebug and Diagnostics

About the role

Key responsibilities & impact

Implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs
Development of innovative DFT IP in collaboration with the multi-functional teams
Enabling the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows
Participating in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die
Crafting solutions and debug with minimal mentorship

Requirements

What you’ll need

Bachelor's or a Master's Degree in Electrical or Computer Engineering required
At least 5 years of experience
Prior experience working in the latest innovative trends in DFT, test and silicon engineering
Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan
Experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
Experience working with Gate level simulation, debugging with VCS and other simulators
Post-silicon validation and debug experience
Ability to work with ATE patterns, P1687

Benefits

Comp & perks

Medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
Paid parental leave
Short and long-term disability coverage
Basic life insurance
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
Paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year for non-exempt employees
Flexible vacation time off program for exempt employees
80 hours of sick time off provided on hire date and each January 1st thereafter
Up to 80 hours of unused sick time carried forward from one calendar year to the next
Optional 10 paid days per full calendar year to volunteer