MBIST Technical Leader

Cisco

ASIC Technical Lead in Silicon One team developing cutting edge networking chips for Cisco. Leading MBIST methodology and architecture design for silicon one chips.

Posted 7/2/2026full-timeSan Jose • California, Texas • 🇺🇸 United StatesSenior💰 $210,600 - $305,100 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in MBIST methodology and architecture design for silicon one chips, with a strong focus on memory architectures and DFT tools. Proven ability to define requirements and execute complex test strategies to enhance silicon quality and yield.

Highest-signal resume keywords

MBIST Methodology LeadershipASIC DFT ExperienceMemory Architecture KnowledgeScripting Skills (Python, TCL, Perl)Industry-Standard DFT Tools Experience

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

MBIST Architecture DesignASIC DFTMemory Architectures (SRAM, DRAM)Test Strategy ExecutionVerilog/System Verilog

Soft Skills

Excellent Communication SkillsCross-Team Collaboration

Tools & Technologies

Synopsys DesignWareSMSTestMaxMentor Graphics Tessent

Industry Keywords

Silicon QualityYield ImprovementFailure ModesAdvanced Technology Nodes

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

lead the MBIST methodology in silicon one chips
design & implement robust and reusable MBIST architecture
spec comprehensive MBIST architecture and implementation agnostic to technology and tools
define MBIST requirements for advanced technology nodes & packages

Requirements

What you’ll need

Bachelors in Electrical engineering plus at least 12+ years (or Master's with 10+ years) experience in ASIC DFT
prior experience with memory architectures (SRAM, DRAM, etc.) and failure modes
prior experience with industry-standard DFT tools (e.g., Synopsys DesignWare, SMS, TestMax, Mentor Graphics Tessent)
scripting skills (Python, TCL, Perl) for automation
ability to plan and execute complex test strategies
excellent communication skills for cross-team collaboration
focus on silicon quality and yield improvement
preferred: experience in Verilog/System Verilog and addressing Memory failure correlation in production

Benefits

Comp & perks

medical, dental and vision insurance
401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays plus 1 floating holiday
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time for non-exempt employees
flexible vacation time off program for exempt employees
80 hours of sick time off
additional paid time away for family emergencies
optional 10 paid days per year for volunteering
eligibility for annual bonuses