ASIC Engineering Technical Lead – DFT

Cisco

ASIC Engineering Technical Lead focused on Design-for-Test, leading DFT solutions for next-generation ASICs. Responsible for implementation of test architectures and silicon validation at Cisco.

Posted 7/9/2026full-timeRemote • Vermont • 🇺🇸 United StatesSenior💰 $149,100 - $218,900 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in leading the development and implementation of Design for Test (DFT) solutions for ASICs, including scan insertion, compression logic, and memory/logic Built-In Self-Test (BIST). Proficient in generating ATPG test patterns and providing post-silicon testing and validation support.

Highest-signal resume keywords

DFT Architecture ImplementationScan InsertionATPG Test Pattern GenerationASIC Design ValidationVerilog/System Verilog Integration

ATS Keywords

Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills

DFT Solutions DevelopmentScan InsertionCompression LogicMemory BISTLogic BISTATPG Test Pattern GenerationRTL DebuggingSimulation RunsPython ProgrammingTcl Programming

Tools & Technologies

ATE TestersScan Design Rule Check (DRC) Tools

Industry Keywords

ASICsSilicon Failure DebugPost-Silicon TestingHigh Speed Technology NodesLow Power Consumption

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

leading development of DFT solutions for next-generation ASICs
Lead implementation of SSN, hierarchical test flow DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST
Generate and deliver ATPG test pattern for stuck-at, transition, cell aware and path delay fault models
drive scan-based diagnosis methodology for Silicon failure debug
provide post-silicon testing and validation support
evaluate design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
Perform simulation runs and debug for non-timing and back annotated timing (SDF) gate level simulations
Develop test scripts, automate processes, and analyze data using programming languages such as Python, Tcl, or C++

Requirements

What you’ll need

Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
Prior experience working with ASICs
Prior experience in scan insertion and DFT setup, integration and validation
Prior experience implementing DFT architectures—including scan insertion, compression/decompression logic, and memory/logic BIST.
10+ years of experience working with ASICs (preferred)
10+ years of experience in scan insertion and DFT setup, integration and validation (preferred)
Experience driving ASIC DFT execution from concept through tapeout (preferred)
Experience working with ATE testers and test teams (preferred)
RTL experience to understand and debugging issues pertaining to DFT (preferred)
Ability to solve complex problems including clock domain crossings (preferred)
Familiar with advanced silicon process and technology nodes for high speed and low power consumption (preferred)
Strong implementation or integration of design blocks using Verilog/System Verilog (preferred)

Benefits

Comp & perks

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year
flexible vacation time off program
80 hours of sick time off provided on hire date
up to 80 hours of unused sick time carried forward
Optional 10 paid days per full calendar year to volunteer