Intel Corporation

Engineer

• Develop ESD/LU rule decks aligned with the ESD Design Rule Manual and reliability requirements
• Create and maintain reliability ESD and LU design rule methodologies and specifications
• Collaborate with internal design, reliability, and CAD teams to define and implement new tool features
• Build and execute test cases for rule debugging, validation, and signoff
• Define QA requirements and drive related automation to improve robustness and efficiency of rule checks
• Lead innovation initiatives to enhance existing ESD/LU verification automation, tools, and methodologies
• Identify and analyze ESD/LU design problems, define root causes, and drive solutions across teams

Senior EDA Tools Engineer – ESD

Designer

• Develop and execute comprehensive mixed-signal IP verification plans to ensure designs meet specifications
• Create and maintain test benches and verification environments using advanced methodologies such as UVM and OVM
• Perform analog behavioral modeling to validate design functionality, timing, and power objectives
• Identify, replicate, and debug presilicon bugs, root cause issues, and drive corrective measures
• Analyze coverage metrics to ensure verification completeness and propose improvements where needed
• Collaborate across disciplines to refine verification strategies, optimize designs, and achieve project goals
• Document test plans, methodologies, and results, and lead technical reviews with cross-functional teams
• Maintain and enhance existing verification infrastructure and methodologies to support evolving design challenges

IP Design Verification Engineer

• Join Intel as a Yield Development Engineer and play a pivotal role in advancing semiconductor process technology.
• Drive yield improvements across next-generation technology nodes.
• Work with cross-functional teams to tackle complex engineering challenges and develop innovative solutions.
• Identify and resolve yield-limiting factors throughout technology node lifecycles.
• Conduct advanced statistical analysis and create data visualizations.
• Partner with design, test, and process development teams to debug yield issues.
• Lead new product introductions and design-technology co-optimization initiatives.
• Ensure manufacturability through comprehensive process analysis.

Yield Development Engineer

Software Engineer

• Develop and execute commodity strategies that meet Intel's technical, cost, quality, availability, and sustainability requirements.
• Build and manage relationships with suppliers to drive innovation, improve performance, and ensure alignment with Intel's long-term business objectives.
• Lead supplier negotiations, including terms, conditions, and pricing, to achieve favorable outcomes for Intel.
• Collaborate with cross-functional teams, including engineering, finance, and legal, to address purchasing requirements and resolve disputes.
• Analyze evolving market conditions and implement strategic pivots to ensure business continuity and risk mitigation.
• Define and negotiate technical contract terms to meet both Intel's and supplier capabilities.

Engineering Commodity Manager

Mechanical Engineer

• Develop logic design and register transfer level (RTL) coding for IP blocks using languages such as System Verilog and Verilog
• Optimize logic designs to meet power, performance, area, and timing goals
• Participate in defining architecture and microarchitecture features for IP blocks
• Collaborate with cross-functional teams to review verification plans, ensuring comprehensive validation of design features
• Identify and resolve failures in RTL tests, implementing corrective measures to ensure design correctness
• Apply power-saving techniques such as clock gating and power gating to enhance energy efficiency
• Support System-on-Chip (SoC) customers with the integration and verification of IP blocks, ensuring high-quality handoff and smooth execution
• Use industry-standard tools and methodologies to ensure design integrity and compliance with quality assurance standards

IP Logic Design Engineer

• Test bench development
• directed/constrained random test generation in UVM
• Closely working with design team to review specifications and architecture, define verification plan, coverage, and improve methodology
• Run RTL and gate level functional verification, debug failures, and analyze coverage
• Support mixed-signal verification using Verilog models of analog IP

• Design and develop complex analog and mixed-signal circuits
• Perform circuit design, simulation, and optimization
• Execute analog block floor-planning and extract chip parameters
• Develop and implement test plans to verify circuit designs
• Conduct post-layout simulations with extracted parasitics
• Collaborate cross-functionally with architecture, layout, and validation teams
• Evaluate experimental test data and iterate designs

Analog Circuit Design Engineer

Operations

• Lead and manage the planning and execution of technology projects and programs, ensuring alignment with business objectives and systems requirements.
• Partner with a broad network of experts to lead supply chain planning capability analyses and design.
• Cross-functional collaboration to develop comprehensive project plans ensuring alignment of resources to program scope, schedules, and budget.
• Integrate industry standards to optimize Intel's supply chain.
• Develop and document business processes and training material.
• Lead implementation processes including testing, training, change control, and transition management.
• Proactively identify and address challenges/risk to ensure timely high-quality outcomes.
• Conduct project close-out assessments, documenting lessons learned and providing recommendations for future improvements.

Sales and Operations Planning Business Architect

• Define, design, and implement CPU microarchitecture features
• Develop and deliver RTL (SystemVerilog/Verilog) for CPU IP blocks
• Drive power, performance, and area (PPA) optimization
• Design and validate multi-clock domain and CDC solutions
• Contribute to CPU power management features

Senior CPU RTL Design Engineer – Power Management

• Develop high-quality logic designs, including Register Transfer Level (RTL) coding and simulations, for innovative SoCs
• Collaborate with architects to define and implement microarchitecture features of SoC blocks
• Integrate and validate Intellectual Property (IP) blocks and subsystems into full-chip SoC designs
• Perform quality checks and optimize designs to meet power, performance, area, and timing objectives
• Review verification plans to confirm design features are thoroughly verified
• Employ secure development practices to mitigate security risks
• Work with IP providers to integrate and validate IPs at the SoC level
• Drive quality assurance compliance to enable efficient IP-SoC handoffs

SoC Logic Design Engineer

Full-stack Engineer

• Design, develop, and enhance software tools and automation solutions that support engineering workflows in advanced packaging and silicon enablement
• Apply AI/ML techniques end-to-end to improve tool capability, automation, decision support, and workflow efficiency
• Build and integrate intelligent features into software systems, including data-driven automation, predictive capabilities, and workflow optimization
• Collaborate closely with engineering, research, and product teams to understand requirements and translate them into scalable technical solutions
• Contribute to the architecture, design, implementation, testing, and deployment of AI/ML-enabled software tools
• Develop robust, maintainable, and production-quality code in a fast-paced development environment
• Evaluate new AI/ML technologies, frameworks, and approaches to drive innovation in engineering productivity and automation
• Support experimentation, prototyping, and iterative refinement of new solutions in a research-focused setting
• Ensure software solutions are reliable, scalable, and aligned with engineering and business goals
• Participate in code reviews, design discussions, and cross-functional technical problem-solving

• Perform physical design implementation of custom IP and SoC designs from RTL to GDS.
• Execute comprehensive physical design flows, including synthesis, floor planning, place and route, clock tree synthesis, static timing analysis, and power/clock distribution.
• Conduct verification and signoff activities such as formal equivalence verification, static timing analysis, power integrity analysis, and layout verification.
• Analyze results to identify and resolve violations related to timing, reliability, and design structure.
• Optimize designs for power, performance, and area using industry-standard EDA tools.
• Develop and refine physical design methodologies and flow automation to improve team efficiency and accuracy.
• Collaborate with teams to address design challenges and deliver robust solutions.

Physical Design Engineer

Application Engineer

• Directly engaging customers to provide support for customer developed systems including providing on-site power on support
• Participating in the defining and development of Proof-of-Concept systems (and demos)
• Replicating and debugging customer reported platform issues
• Development and presentation of technical collateral to customers, ecosystem providers, and the sales channel
• Working directly with platform and chipset software architects to develop and finalize platform hardware requirements
• Participate in new product and program meetings
• Participate in customer platform schematic and layout reviews
• Provide support to analysis teams in the context of field quality return issues
• Making use of laboratory measurement equipment during debug activities
• Operate Linux based machines and tools in-order-to build and flash SW components and facilitate debug activities

Hardware Platform Applications Engineer – Military & Aerospace

Field Engineer

• Serve as the technical interface for customers evaluating or implementing DSP solutions in Altera FPGAs
• Provide architecture guidance, system-level design recommendations, and performance optimization strategies
• Lead technical discussions and solution positioning with engineering teams and decision-makers
• Collaborate with Sales and FSEs to identify, qualify, and drive DSP-related opportunities
• Demo, present, and position DSP architectures using IP and tools such as DSP Builder (via MATLAB/Simulink)
• Support customers through the full design cycle—from concept to production
• Provide deep expertise in digital signal processing concepts (e.g., filtering, channelization, beamforming, RF/DSP chains)
• Debug and resolve complex system and application-level issues
• Develop reusable architectures, demonstrations, and design collateral to scale DSP engagement efficiency
• Partner with Altera’s Aerospace, Defense and Government (ADG) group to support DirectRF opportunities
• Identify and define appropriate RF+DSP architectures to support customer requirements
• Deliver internal and customer-facing training on DSP solutions, tools, and design methodologies
• Contribute to application notes, reference designs, and solution documentation

DSP Specialist, Field Applications Engineer – West Region

• Execute comprehensive power and performance (PnP) validation for systems and subsystems
• Develop and implement innovative design for debug (DFD) tools and automation scripts
• Conduct thorough root cause analysis to resolve complex triage failures and performance bottlenecks
• Collaborate effectively with cross-functional teams for SoC debug readiness
• Formulate comprehensive debug requirements and validation strategies for new product features
• Design, develop, and execute test methodologies to validate functionalities and power states
• Utilize advanced scripting and automation techniques for efficient analysis and optimization

Senior EDA Tools Engineer – ESD

IP Design Verification Engineer

Yield Development Engineer

Engineering Commodity Manager

IP Logic Design Engineer

IP Design Verification Engineer

Analog Circuit Design Engineer

Sales and Operations Planning Business Architect

Senior CPU RTL Design Engineer – Power Management

SoC Logic Design Engineer

Software Engineer

Physical Design Engineer

Hardware Platform Applications Engineer – Military & Aerospace

DSP Specialist, Field Applications Engineer – West Region

SoC Debug – Post-Silicon PnP Validation Engineer