Intel Corporation

Full-stack Engineer

• Design and build the agent loop: planning, tool invocation, observation handling, retries, termination
• Implement tool integrations — file I/O, terminal / shell execution, web, MCP servers, message apps
• Build context management: what goes in the window, when to summarize, how to use long / cross-session memory
• Implement scheduling and automatic / background task execution
• Keep the harness model-agnostic so local and cloud models are swappable behind one abstraction
• Design agent security mechanisms through different approaches
• Make the loop observable, debuggable: tracing, replay, and reproducible agent sessions

Software Engineer – Agent Harness

Machine Learning Engineer

• Build evaluation benchmarks and metrics
• Build and iterate on agent harness, including context engineering, agent memory, tools, skills
• Develop robust, reproducible training workflows from data ingestion and preprocessing through model checkpointing and deployment
• Design RL environments and reward functions
• Debug and optimize training runs
• Conduct training runs to improve model capabilities for agentic applications

Engineer

• Optimize inference engines (llama.cpp, vLLM) for constrained local and edge environments
• Profile and optimize local inference for latency, throughput, and memory on edge hardware
• Tune KV cache, continuous batching, and scheduling for interactive agent workloads
• Drive quantization strategy and validate quality impact
• Cut CPU overhead and improve engine startup, model load, and lifecycle
• Benchmark across hardware tiers and publish performance comparisons
• Upstream fixes and patches to open-source engines

Inference Optimization Engineer – Local, Edge Runtime

• Provide senior technical leadership to ensure the reliability, safety, and performance of critical mechanical systems.
• Serve as the mechanical subject matter expert for critical environments.
• Provide technical guidance and direction to ensure system reliability, operational resilience, maintainability, and lifecycle performance.
• Mentor and guide junior mechanical engineers.
• Act as shutdown coordinator for cross-discipline major electrical and mechanical shutdowns.
• Develop and lead mechanical reliability programs using performance trending, KPI development, and root cause analysis.
• Evaluate system health, capacity, and lifecycle risk.
• Act as the principal mechanical system owner for operational and project-related mechanical systems.
• Maintain working knowledge of electrical power infrastructure to understand cross system dependencies.
• Serve as the single Intel Fire and Life Safety (FLS) system owner and primary point of contact for Mission Campus.
• Provide mechanical engineering oversight during design, construction, commissioning, and turnover of projects.

Senior Data Center Facilities Engineer

Solutions Engineer

• Partner with customers and Business Development to design tailored Intel Foundry solutions
• Support the full sales cycle from engagement through delivery
• Provide technical leadership in presentations, demonstrations, and solution design discussions
• Develop proposals, reference architectures, and proof-of-concept solutions
• Collaborate with engineering teams to validate feasibility and optimize designs
• Drive competitive positioning, pricing, and contract negotiations
• Deliver technical documentation, implementation roadmaps, and risk mitigation plans
• Build deep knowledge of Intel Foundry Services, roadmaps, and IP offerings
• Stay current on industry trends, regulatory requirements, and USG/DIB market dynamics
• Understand semiconductor supply chain, pricing models, and contract structures
• Establish trusted advisor relationships with customer technical stakeholders
• Partner across engineering, business development, and marketing teams
• Translate customer needs into actionable technical and business solutions
• Contribute market insights to influence product and roadmap strategy
• Identify, qualify, and advance new business opportunities
• Support win strategies, competitive positioning, and deal execution
• Manage technical sales activities through contract negotiation and close
• Maintain accurate pipeline tracking and forecasting in CRM systems
• Develop technical collateral for U.S. Government and defense markets
• Support marketing initiatives and customer success storytelling
• Represent Intel at industry events as a technical subject matter expert
• Drive initiatives to expand market reach and customer value realization

Foundry Solutions Architect

Sales

• Provides leadership and management of the direction, planning, and execution of sales activities for expanding its sales achievement in area of Military, Industry, Automotive, Medical and Consumers.
• Works with Asia Pacific Management and corporate headquarters as appropriate to manage all aspects of the responsible area’s business.
• Develop a vision of what the Channel Sales team should be and how we can better penetrate the market.
• Pull entire organization forward and drives output from other teams outside of Sales: Technical support, Marketing and QA.
• Works closely with corporate headquarters and distributors to eliminate potential roadblocks to business development.
• Takes ownership of corporate policies and define own policies where absent.
• Establish a culture of ownership by setting goals, driving execution, monitoring metrics, and adjusting (PDCA).
• Manage Distributor hiring, training, and terminations to improve the quality of the Sales.
• Facilitate and foster consistent communication and good working relationship between the Corporate Sales team Distributor Sales teams and other teams across the Company worldwide.
• Builds executive relationship with key customers and mentors staff to do same.
• Lead team to successfully execute against a plan to sell all products/services.
• Generate Business plan for Broad accounts including opportunity mapping, competitive analysis, and organization mapping.

Senior Channel Sales Manager, Asia Pacific

Frontend Engineer

• Demonstrated leadership and hands-on experience in leveraging AI tools and methodologies to drive significant efficiency gains and improvements in RTL coding and other areas of silicon development.
• Proactively advances front-end methodologies and contributes to architectural and microarchitectural discussions to enhance scalability and flexibility.
• Develops and implements strategies, tools, and techniques for RTL development and logic optimization, ensuring designs meet power, performance, area, and timing targets, as well as physical design integrity.
• Possesses a comprehensive understanding of both front-end and back-end flows, with a proven track record of delivering solutions across multiple domains.
• Collaborates effectively with architecture, backend, and other design teams to deliver industry-leading products.
• Builds and sustains a high-performing, technically strong organization by fostering and upholding core group values, norms, and behaviors.

Senior CPU RTL Front End Methodology Engineer

Program Manager

• Drive end‑to‑end supply chain execution supporting customer and business commitments.
• Translate demand signals, forecasts, and supply changes into coordinated operational actions across internal teams and partners.
• Ensure execution and follow‑through of purchase requisitions and purchase orders in SAP and Ariba, partnering with sourcing and procurement teams as appropriate.
• Track order acknowledgments, lead times, shipment status, and delivery commitments to ensure execution discipline.
• Identify, manage, and resolve execution issues, risks, and constraints impacting supply continuity.
• Support prioritization and escalation of competing operational demands to protect delivery commitments.
• Serve as a strong integrator across planning, procurement, manufacturing, logistics, finance, and systems teams.
• Drive alignment, accountability, and shared ownership across cross‑functional execution workflows.
• Facilitate clear communication and coordination to prevent execution gaps.
• Partner effectively with stakeholders who have different priorities and incentives in a matrixed environment.
• Deliver near‑term results using existing tools, systems, and processes.
• Contribute to improvements in standard work, governance, and execution cadence.
• Support development of scalable, repeatable workflows and operating practices.
• Help strengthen execution reliability as the organization continues to evolve.

Senior Technology Project / Program Manager

Hardware Engineer

• Join Intel's world-class team as an EDA Tools Hardware Engineer
• Play a pivotal role in shaping the future of silicon innovation
• Contribute to the enablement and adoption of cutting-edge hardware design tools, flows, and methodologies
• Enhance the efficiency of design processes and optimize power, performance, and technology node advancements
• Collaborate with EDA vendors, define next-generation design tools, and contribute to groundbreaking innovations

Hardware Engineer, EDA Tools

Designer

• Develop and maintain transistor-level electromigration (EM) and IR drop analysis flows for custom IPs, embedded memories, SRAMs, analog/mixed-signal interfaces, and high-performance custom macros
• Focus on CAD methodology, automation infrastructure, power integrity analysis flows, and silicon correlation for transistor-level reliability verification
• Work closely with circuit design, physical design, package, reliability, and signoff teams to enable scalable and accurate EM/IR analysis methodologies for advanced-node designs

EDA Design Flow Development Engineer

Account Executive

• Influence and advocate Intel-based products and solutions through vertically oriented, solutions-led approaches to businesses and IT decision makers
• Build and maintain C-suite and senior executive relationships, owning executive briefings and sponsorships
• Work with named accounts in specific industry segments to drive transformational strategies and advocate preference for Intel architecture
• Collaborate with Intel resources and partner sales teams to drive product purchases for industry customers
• Manage business and technical relationships with partners including OEMs, cloud service providers, system integrators, and ISVs
• Develop deep understanding of customer technology landscapes to drive digital transformation and identify upselling opportunities
• Meet and exceed financial revenue and forecasting goals through winning tenders and customer deals
• Gather customer feedback and establish recovery action plans to improve overall customer experience
• Contribute to joint marketing activities with enterprise customers

Architect

• Define and lead the architecture strategy for multi-generation, chiplet-based SoC platforms
• Drive modular, scalable SoC design approaches including cross-chiplet coherency and security architectures
• Produce executive-ready architecture options and recommendations for leadership decisions
• Drive functional partitioning across chiplets balancing PPA, D2D bandwidth/latency, validation complexity
• Architect D2D communication for high bandwidth, low latency, and reliability across chiplets
• Define coordinated power delivery and power management flows across chiplets
• Define cross-chiplet error reporting, containment, and recovery policies

Senior SoC Chiplet Architect

• Own end-to-end NSS architecture
• Architect high-performance packet pipelines supporting hundreds of millions of packets/sec throughput
• Lead design decisions for pipeline partitioning, feature scalability, and backward compatibility
• Collaborate across SoC, compute, memory, SW/FW, validation, and customer teams to drive architecture closure

Senior SoC Network Subsystem Architect

Manager

• support IAO IF Intel Foundry transformation
• drive change management activities
• build energy across the Foundry organization
• deliver transformational change that inspires engagement
• collaborate closely with program teams, project managers, end users, employees, managers, and leaders

Change Manager

• Develop ESD/LU rule decks aligned with the ESD Design Rule Manual (DRM) and reliability requirements
• Create and maintain reliability ESD and LU design rule methodologies and specifications
• Collaborate with internal design, reliability, and CAD teams as well as external EDA vendors to define and implement new tool features and requirements
• Build and execute test cases for rule debugging, validation, and signoff
• Define QA requirements and drive related automation to improve robustness and efficiency of rule checks
• Lead innovation initiatives to enhance existing ESD/LU verification automation, tools, and methodologies
• Identify and analyze ESD/LU design problems, define root causes, and drive practical solutions across teams